Design
[Design] Escaping Routing Hell: Partitioning 1.55B Gates (2)
The 128-bit NOC bus refused to cross SLR boundaries. HSTDM partitioning and 16x SerDes closed it at 98.8% LUT.
[Design] Taming 1.55B Gates: Atom Chip FPGA Emulation (1)
A HAPS-100 and nine Xilinx U250 boards, linked by Aurora IP, and the routing wall we hit first.
[Design] Shrinking NPU Shared Memory: 48% Fewer Muxes on a Shared Bus
Moving BIST logic onto a shared bus cut the mux count from 27K to 14K and let the SRAM pack tighter.