https://hj4.it/categories/design/Design · HJ4ITHugoko-KR© CC BY 4.0Sat, 22 Feb 2025 00:00:00 +0000https://hj4.it/posts/atom-chip-emulation-fpga-part2/Sat, 22 Feb 2025 00:00:00 +0000https://hj4.it/posts/atom-chip-emulation-fpga-part2/Hyunje JoDesignFPGAAtom ChipASICEmulationBuilding on Part 1, this post digs into the 128-bit NOC AXI bus bottleneck crossing SLR boundaries inside the VU19P. We used manual HSTDM partitioning and iterative constraint generation to spread read and write channels across the best FPGA locations, and SerDes serialization cut inter-SLR SSI traffic by 16x. The design closed place and route at 80% SSI utilization despite 98.8% LUT consumption.https://hj4.it/posts/atom-chip-emulation-fpga/Fri, 21 Feb 2025 00:00:00 +0000https://hj4.it/posts/atom-chip-emulation-fpga/Hyunje JoDesignFPGAAtom ChipEmulationEngineeringThis post walks through the system we built to emulate the 1.55 billion gate Atom chip: a HAPS-100 carrying four VU19P FPGAs plus nine Xilinx U250 boards linked by Aurora IP. The Neural Engine was offloaded to the U250s while shared memory kept dedicated resources. We pushed back severe routing congestion on the HAPS-100 with AXI bus partitioning, SerDes logic, and manual LVDS bundle mapping.https://hj4.it/posts/rbln-chip-bist/Mon, 01 Jul 2024 21:20:00 +0900https://hj4.it/posts/rbln-chip-bist/Hyunje JoDesignASICMemory ArchitectureDFTAtom ChipThis post details how we optimized NPU shared memory by pulling BIST logic away from the SRAM macros and onto a shared bus, cutting mux count 48% from 27K down to 14K. Applying CPU hardening techniques to the ASIC flow evened out cell density and removed IR drop hotspots, giving wider timing margins and denser SRAM placement than the previous scratchpad-style layout.