[NPU Design Journey] Shared Memory Design and Technical Challenges for Capacity-to-Area Optimization
This post details how optimizing NPU Shared Memory with a Shared Bus interface for MBIST logic reduced Mux count by 48%, resolved timing bottlenecks, and maximized SRAM density.
NPU
Memory Architecture
Scratchpad
![[NPU Design Journey] Shared Memory Design and Technical Challenges for Capacity-to-Area Optimization](/posts/rbln-chip-bist/fig4-shm-dft-logic-distribution.webp)